Power gating is one of the most efficient power consumption reduction techniques. However, when applied in several different\r\nparts of a complex design, functional verification becomes a challenge. Lately, the verification process of this technique has been\r\nexecuted in a Register-Transfer Level (RTL) abstraction, based on the Common Power Format (CPF) and theUnified Power Format\r\n(UPF). The purpose of this paper is to present an OSCI SystemC simulator with support to the power gating design. This simulator\r\nis an alternative to assist the functional verification accomplishment of systems modeled in RTL. The possibility of controlling the\r\nretention and isolation of power gated functional block (PGFB) is presented in this work, turning the simulations more stable and\r\naccurate. Two case studies are presented to demonstrate the new features of that simulator.
Loading....